module flow_led (
    input sys_clk,
    input sys_rst_n,
    output reg [3:0] led
);

(*mark_debug = "true"*) reg [24:0] cnt = 25'b0;

always @(posedge sys_clk or negedge sys_rst_n) begin
    if(!sys_rst_n)
    	cnt <= 25'b0;
    else if (cnt > 25'd12_500_000 - 25'd1)
        cnt <= 25'b0;
    else 
        cnt <= cnt + 25'b1;
end

always @(posedge sys_clk or negedge sys_rst_n) begin
    if(!sys_rst_n)
        (*mark_debug = "true"*)led = 4'b0000;
    else if(cnt == 25'd12_500_000 - 25'd1)
        led = ~led;
    else
    	led = led;
end
    
endmodule